Evolving packet processing by a factor of 1000
Tuesday, October 26, 2021 at 1:15PM Part III: IP routing: The FP5 chipset
Nokia’s FP5 IP router chipset has been a design four years in the making, the latest iteration of a near 20-year-old packet processing architecture.
The 3-device chipset FP5 is implemented using a 7nm CMOS process. The design uses 2.5D stacked memory and is the first packet processor with 112 gigabit-per-second (Gbps) serialiser-deserialiser (serdes) interfaces. Also included are line-rate hardware encryption engines on the device’s ports.
Ken Kutzler
What hasn’t been revealed are such metrics as the chipset's power consumption, dimensions and transistor count.
Ken Kutzler, vice president of IP routing hardware at Nokia IP Networks Division, says comparing transistor counts of chips is like comparing software code: one programmer may write 10,000 lines while another may write 100 lines yet both may execute the same algorithm.
“It’s not always the biggest and baddest chip in the world that compares well,” says Kutzler.
