ECOC '22 Reflections - Part 2

Gazettabyte is asking industry and academic figures for their thoughts after attending ECOC 2022, held in Basel, Switzerland. In particular, what developments and trends they noted, what they learned, and what, if anything, surprised them. 

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In Part 2, Broadcom‘s Rajiv Pancholy, optical communications advisor, Chris Cole, LightCouting’s Vladimir Kozlov, Ciena’s Helen Xenos, and Synopsys’ Twan Korthorst share their thoughts.

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Tencent makes its co-packaged optics move

• Tencent is the first hyperscaler to announce it is deploying a co-packaged optics switch chip

• Tencent will use Broadcom’s Humboldt that combines its 25.6-terabit Tomahawk 4 switch chip with four optical engines, each 3.2 terabit-per-second (Tbps)

Part 2: Broadcom's co-packaged optics 

Tencent will use Broadcom’s Tomahawk 4 switch chip co-packaged with optics for its data centres.

Manish Mehta

“We are now partnered with the hyperscaler to deploy this in a network,” says Manish Mehta, vice president of marketing and operations optical systems division, Broadcom. “This is a huge step for co-packaged optics overall.”

The Chinese hyperscaler will use Broadcom’s 25.6Tbps Tomahawk 4 Humboldt, a hybrid design where half of the chip’s input-output (I/O) is optical and half is the chip’s serialisers-deserialisers (serdes) that connect to pluggable modules on the switch’s front panel.

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Broadcom samples the first 51.2-terabit switch chip

• Broadcom's Tomahawk 5 marks the era of the 51.2-terabit switch chip
• The 5nm CMOS device consumes less than 500W
• The Tomahawk 5 uses 512, 100-gigabit PAM-4 (4-level pulse amplitude modulation) serdes (serialisers-deserialisers)
• Broadcom will offer a co-packaged version combining the chip with eight 6.4 terabit-per-second (Tbps) optical engines

Part 1: Broadcom's Tomahawk 5

Broadcom is sampling the world's first 51.2-terabit switch chip.

With the Tomahawk 5, Broadcom continues to double switch silicon capacity every 24 months; Broadcom launched the first 3.2-terabit Tomahawk was launched in September 2014.

"Broadcom is once again first to market at 51.2Tbps," says Bob Wheeler, principal analyst at Wheeler's Network. "It continues to execute, while competitors have struggled to deliver multiple generations in a timely manner."

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Broadcom discusses its co-packaged optics plans

If electrical interfaces are becoming an impediment, is co-packaged optics the answer? Broadcom certainly thinks so.

One reason for the growing interest in co-packaged optics is the input-output (I/O) demands of switch chips. If the packet processing capacity of such chips is doubling every two years, their I/O must double too.

Alexis BjörlinRepeatedly doubling the data throughput of a switch chip is a challenge.

Each new generation of switch chip must either double the number of serialiser-deserialiser (serdes) circuits or double their speed.

A higher serdes count - the latest 25.6-terabit switch ICs have 256, 100 gigabit-per-second serdes - requires more silicon area while both approaches - a higher count and higher speed - increase the chip's power consumption.

Faster electrical interfaces also complicate the system design since moving the data between the chip and the optical modules on the switch's front panel becomes more challenging.

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Enabling 800-gigabit optics with physical layer ICs

Broadcom recently announced a family of 800-gigabit physical layer (PHY) chips. The device family is the company’s first 800-gigabit ICs with 100-gigabit input-output (I/O) interfaces.

Source: Broadcom

Moving from 50-gigabit to 100-gigabit-based I/O enables a new generation of 800-gigabit modules aligned with the latest switch chips.

“With the switch chip having 100-gigabit I/Os, PHYs are needed with the same interfaces,” says Machhi Khushrow, senior director of marketing, physical layer products division at Broadcom.

Broadcom’s latest 25.6 terabit-per-second (Tbps) Tomahawk 4 switch chip using 100-gigabit I/O was revealed at the same time.

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Broadcom’s 14.4-terabit Jericho2c+ router chip

The inexorable growth of IP traffic is being driven by ever more powerful devices being connected to the network and greater numbers of machines talking to each other.

In turn, Covid-19 has contributed its own traffic spike: AT&T reported that in September its core network traffic was 20 per cent up compared to March’s figures.

Jericho2c+ architecture. Source: Broadcom

The growth means that each new generation of router platform must at least double the traffic throughput while keeping the power consumption fixed.

This is a considerable challenge but one that the router chip designers continue to meet.

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Ranovus outlines its co-packaged optics plans

Part 2: Odin technology

Ranovus has tested a chiplet that combines electronics and silicon photonics. Dubbed Odin 8, the monolithic design is targetting the co-packaged optics opportunity, enabling silicon chips to communicate optically.

The company is developing two such chiplets: the 800-gigabit Odin 8 and the higher-capacity Odin 32 that supports 3.2 terabits of traffic. 

Hamid Arabzadeh 

The first use of Odin 8 will be for 800-gigabit client-side modules. “We already have three lead customers for our 800-gigabit module business,” says Hamid Arabzadeh, CEO of Ranovus.

The 800-gigabit pluggable modules using the Odin 8 are expected to be generally available from late 2021.

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