Next-generation PCIe doubles lane speed again, but design challenges mount as AI reshapes interconnect needs.
The Peripheral Component Interconnect Special Interest Group (PCI-SIG), a 1,000-plus-member organisation that oversees the specification work of the long-established PCI Express (PCIe) bus used across industries, is progressing to specify the next version of the standard.
Source: PCI-SIG
Dubbed PCIe 8.0, the newest standard will double the bus's speed per lane to 256 giga-transfers per second (GT/s), twice the transfer rate of the PCIe 7.0 standard ratified in June. First PCIe 7.0-based products are expected next year.
In the data centre, PCIe is used by general-purpose processors in servers and AI accelerator clusters, connecting processors to storage and network interface cards (see chart above).
The specification of the newest version of the PCIe bus poses significant design challenges. Yet despite the challenges posed by moving to the next speed doubling, Al Yanes, PCI-SIG president and chairperson, expects PCIe 8.0 to be completed on schedule in 2028. "We have very good confidence that we can do 256-gig on copper," he says.
The purple graph shows the typical three-year development cycle of each generation of the PCIe bus while the green line indicates industry demand, according to PCI-SIG. Source: PCI-SIG
Design challenges
Doubling the data rate per bus lane means faster signals over a copper channel. The doubling of transfer speed shortens the achievable signal reach and places demands on the design of connectors, while requiring advanced and costly printed circuit board materials. "All the things required to make these interfaces run so fast," says Yanes.
It is likely that more retimer ICs will be needed to satisfy reach requirements along with advanced copper cabling as an alternative to traces on a printed circuit board. In turn, PCIe-over-optical will play a role for longer reaches. PCIe 8.0 will also require new test and measurement procedures.
A strength of the PCIe protocol is its backwards compatible, all the way to the first PCIe 1.0 that operates at 2.5GT/s. "But do we really need to go that far back?" says Yanes. "There are always going to be these questions and challenges that the Work Group will face, trying to run at these crazy frequencies."
Given the early status of the PCIe 8.0 work – now at Version 0.3, the first review draft – these remain open questions. Acknowledging the standard’s early development stage, Yanes concedes: “We are not as smart as we are going to be a year from now.”
PCIe and AI
PCIe used in AI systems typically connects the host processor (CPU) to AI accelerators (GPUs) and to network interface cards (NICs) to allow GPUs to connect to the scale-out network. The PCIe bus is also used as the physical layer when the CXL protocol is used with memory. However, with alternative schemes being adopted, does PCIe risk playing a diminishing role in AI?
“Tightly-coupled AI designs are already replacing PCIe with alternatives, such as Nvidia using NVLink to connect CPUs and GPUs,” says Bob Wheeler, principal analyst at Wheeler’s Network. “On the other hand, PCIe remains the underlying physical layer for some protocols such as AMD’s Infinity Fabric and Amazon’s NeuronLink. Increasingly, however, AI interconnects are adopting Ethernet-style physical layers that already operate at 200Gbps per lane."
Yanes admits it is essential to be fearful and challenge the PCI-SIG's work to ensure it remains relevant. He welcomes the recent wave of OpenAI investments in hardware companies that promote more AI system options. "That is good for us, we are a standards organisation," he says. "It helps us compete when there are different solutions for AI."
While PCIe 8.0 is scheduled for completion in 2028, Yanes says that if AI’s scaling trajectory continues, PCI-SIG members could press to accelerate its release.
PCIe protocol explained
The PCIe bus uses point-to-point communications based on a simple duplex scheme, with serial transmissions in both directions, which is referred to as a lane. The bus can be bundled in various lane configurations - x1, x2, x4, x8, x12, x16 and x32 - with x4, x8 and x16 being the configurations most used.
Source: PCI-SIG
The history of PCIe is a long one. The first two PCIe versions, 1.0 and 2.0, delivered 2.5 and 5GT/s per lane per direction, respectively. A transfer refers to encoded bits. The first two PCIe versions use an 8b/10b encoding scheme such that for every ten-bit payload sent, 8 bits are data. This is why the data transfer rates per lane per direction are 2Gbps and 4Gbps (250 and 500 gigabytes per second or GB/s), respectively.
With PCIe 3.0, engineers decided to increase the transfer rate to 8GT/s per lane, and assumed that no equalisation would be needed to counter inter-symbol interference. However, equalisation was required, which explains why PCIe 3.0 adopted 8GT/s and not 10GT/s. Another PCIe 3.0 decision was to move to a 128b/130b scheme to reduce the encoding overhead from 20 per cent to over 1 per cent. PCIe 4.0 and following rates have each doubled the transfer rate. PCIe 4.0 is at 16GT/s while PCIe 7.0 is now at 128GT/s.
Meanwhile, PCI 8.0 will operate at 256GT/s, equating to 32GB/s. This is why, when a 16-lane PCIe bus will be used, 512GB/s can be sent in each direction for a total transfer rate of 1TB/s.
Another development of note was PCIe 6.0's adoption of 4-level pulse amplitude modulation (PAM-4), also the signalling scheme used for PCIe 7.0 and PCIe 8.0.