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Entries in GPU (3)

Thursday
Feb212019

Ayar Labs prepares for the era of co-packaged optics 

The first of two articles on co-packaged optics.

Part 1: Ayar Labs

Ayar Labs is readying its co-packaged optics technology for scaled production in the second half of 2020. So says CEO Charlie Wuischpard who joined the start-up in late 2018 after it secured $24 million in funding to bring its products to market.

Co-packaged optics refers to the intimate coupling of optics with an ASIC in one package. Such tightly-coupled optics promises to overcome the growing system challenges associated with linking an ASIC’s high-speed signals to pluggable optics residing on a platform’s faceplate.

Charlie Wuischpard Wuischpard joined Ayar Labs from Intel where he led the supercomputing segment within the company’s data centre group. Wuischpard also led Intel’s disaggregated rack initiative.

“In both these, silicon photonics plays a huge role in enabling future architectures and future designs,” he says.

Ayar Labs raised its funding after demonstrating successfully its optical designs: a silicon-photonics optical chiplet, dubbed Teraphy, and its Supernova external laser source. 

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Friday
Oct052018

PCI Express back on track with latest specifications 

Richard Solomon and Scott Knowlton are waiting for me in the lobby of a well-known Tel-Aviv hotel overseeing the sunlit Mediterranean Sea.  

Richard SolomonSolomon, vice chair of the PCI Special Interest Group (PCI-SIG), and Knowlton, its marketing working group co-chair, are visiting Israel to deliver a training event addressing the PCI Express (PCIe) high-speed serial bus standard. 

With over 750 member companies, PCI-SIG conducts several training events around the world each year. The locations are chosen where there is a concentration of companies and engineers undertaking PCIe designs. “These are chip, board and systems architects,” says Solomon. 

PCI-SIG has hit its stride after a prolonged quiet period. The group completed the PCIe 4.0 standard in 2017, seven years after it launched PCIe 3.0. The PCIe 4.0 doubles the serial bus speed and with the advent of PCIe 5.0, it will double again.

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Wednesday
Dec102014

FPGAs embrace data centre co-processing role

Part 1: Xilinx's SDAccel development tool


The PCIe accelerator card has a power budget of 25W. Hyper data centres can host hundreds of thousands of servers whereas other industries with more specialist computation requirements use far fewers servers. As such, they can afford a higher power budget per card. Source: Xilinx

Xilinx has developed a software-design environment that simplifies the use of an FPGA as a co-processor alongside the server's x86 instruction set microprocessor.

Dubbed SDAccel, the development environment enables a software engineer to write applications using OpenCL, C or the C++ programming language running on servers in the data centre.   

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